As it is well known in recent years the development of power devices has been considerably accelerated under the pressure of two different factors: the increase in the functions which can be integrated in a single chip or die wherein the power device is realized; and the increasing miniaturization of electronic devices for applications on portable devices such as personal computers, mobile phones and the like.
In fact, miniaturization has been the motivation of many mass products and presently around 50% of electronic systems can be branded as “portable” and this percentage will certainly and drastically increase in next years. Miniaturization requirements obviously impact on the size and weight of these electronic devices. In particular, the highest ratio between the chip or die size and the footprint thereof moved from around 0.3 in the early nineties to around 0.8 at the end of the century.
On another hand, the continuous developments in the microprocessor technology have also led to an increase in the power device operating frequency thus increasing the speed and field of application thereof. To keep or even increase the power of electronic power devices at high operating frequencies there is the need to increase the current provided to the devices and thus the density of the power distributed on the printed circuit board whereon they are assembled. As a consequence, there is the need to provide electronic power devices with lesser and lesser both static and dynamic power losses to improve the efficiency thereof at the required frequencies.
In this context it may be very important to reduce or remove also the printed circuit board parasitic components that can add losses to the whole electronic system. In the specific case of vertical conduction power devices better performance can be obtained by reducing the device output resistance as well as the parasitic capacitances and the thermal resistance.
In fact, as it is well known, a Q-factor (FFOM) to evaluate the efficiency of a vertical conduction electronic power device is the product of the output resistance (Ron) and the device footprint. Moreover, for high frequency applications the dynamic feature represented by an electric charge value to be provided to the conduction terminal (Gate change) to turn the device on or off is important. The lower the value of the product of the three indicated factors (Ron, Footprint, Gate change), the more efficient the device is.
It is also known that vertical conduction electronic power devices are usually assembled on printed circuit boards through surface assembly methods and it is thus preferable that they have all conduction terminals on a same plane. In this perspective, methods to realize vertical conduction devices suitable to draw all conduction terminals on a same surface plane have been developed, without penalizing the three above-mentioned Q-factors and particularly the output resistance.
A first approach is represented by a power device realized by a conveniently shaped metal container or frame suitable to draw at the same level in an upper surface, the device conduction terminal (drain) located on a lower surface. An embodiment thereof is shown in FIG. 1 and described in the document MOSFET (metal oxide semiconductor field effect transistor BGA (ball grid array) design—Fairchild Semiconductor—August 2002. In this document, a method is described for realizing a power device comprising an assembly step wherein the device integrated on the semiconductor (die) is welded inside a frame through conventional so-called die attach techniques.
Although somewhat advantageous under several aspects, the approach has the drawback that the leveling of conduction terminals (source, gate) located on the device upper surface with the conduction terminal (drain) located on the opposite surface, and drawn on this surface, is ensured in the absence of the frame mechanical tolerances, of the semiconductor chip thickness as well as of the thickness of the welding compound used for the die attach technique. Therefore this approach may not be sufficiently reliable for the realization of large-scale-efficiency vertical conduction power devices.
A second known approach, commonly indicated with the term WLCSP (Wafer Level Chip Scale Package), provides for the complete removal of the metal frame by realizing a package immediately on a silicon chip, whereon a plurality of dies are integrated, before splitting the single dies. In the realization of vertical conduction devices having overlapped dies, conduction terminals are drawn on a same device surface. This approach provides the realization of deep sinkers, along the die outer perimeter, crossing the whole silicon chip thickness, which are filled with a conductive material such as a metal (for example gold).
Also this second known approach, although advantageous under several aspects, has the drawback that the current flow, coming from the terminal located in the die lower surface, can be collected only along the outer perimeter of the device upper surface. This implies that the resistive contribution due to the current flow path on the substrate is considerable. Moreover, the provided realization method is very complex and thus rarely used.
It is also known to realize a vertical conduction power device through the so-called Flip Chip BGA (Ball Grid Array) technique providing that “bumps”, made of tin-based welding alloys, are positioned on the chip conduction pads, to allow the same to be directly connected on the board (FIG. 2). This technique requires that a wettable metal is arranged on the pads.
The Flip Chip BGA technique is used in US patent application no. US 2001/0045635 by Kinzer wherein the device drain is brought to the surface by deep and heavily-doped sinkers or sinkers filled with a conductive layer (metal or polysilicon) creating conductive paths between the substrate and the metallization on the device surface (FIG. 3). Sinkers are located along the device perimeter and the current flow from the die centre towards the perimeter only relies on the conductive substrate made of heavily-doped silicon.
This third known approach has however the drawback that sinkers are realized along the device perimeter and the substrate, mainly when large-sized, gives a considerable resistive contribution which, in the case of application to low-voltage electronic power devices (20, 50 Volt), has unacceptable values. Moreover in this known approach the contact area with the printed circuit board is reduced, since it is limited to the bumps.